Modern semiconductor chips containing integrated circuits are susceptible to ion contamination wherein ions penetrate the edge of the substrate and migrate into the interior of the chip. These ions interact with the integrated circuits and adversely affect their performance characteristics. Such ion penetration and migration is particularly enhanced when the device is in use due to the existance of electrical fields associated with the active components of the integrated circuits. One structure in common use to reduce ion mobility into the substrate is what is commonly called an edge seal.
Edge seals typically include a highly doped region formed in the substrate which extends completely around the periphery of the chip thereby encircling the area of the chip containing the integrated circuits. A metal layer is then formed over the doped region and in ohmic contact therewith. This two part edge seal, having a positive potential applied thereto, effectively traps mobile ions thereby preventing their continued migration into active areas of the integrated circuits.
It has been recent practice by some to utilize the metal portion of the two part edge seal as an electrical conductor to distribute power to various portions of the integrated circuits. Such use is particularly attractive when the devices to be powered in this manner are located in an area relatively close to the periphery of the chip. In large scale integration circuits the input/output devices are usually most conveniently located in this peripheral area. The output devices usually require significant amounts of power to drive external circuitry. As the power requirement of the output devices increases, the current carrying capability of the metal portion of the two part edge seal becomes a limiting factor.
Since the metal portion of the two part edge seal is formed concurrently with the other metalized conductors of the device, its thickness is necessarily limited to that of these other conductors. In order to increase the current carrying capacity of the edge seal, the metal portion is usually made wider. While this increases current carrying capacity, it also requires that the chip be made larger or the area reserved for integrated circuits be made smaller. Both of these results are undesirable for obvious reasons. What is needed is a structure wherein the current carrying capacity of the metal portion of the two part edge seal is significantly increased while preserving the physical size of the chip and associated integrated circuits.